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HD74LV74A
Dual D-type Flip Flops with Preset and Clear
REJ03D0312-0300Z (Previous ADE-205-244A (Z)) Rev.3.00 Jun. 02, 2004
Description
The HD74LV74A has independent data, preset, clear, and clock inputs Q and Q outputs in a 14 pin package. The input data is transferred to the output at the rising edge of clock pulse CLK. Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the low-power consumption extends the battery life.
Features
* * * * * * * VCC = 2.0 V to 5.5 V operation All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25C) Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25C) Output current 6 mA (@VCC = 3.0 V to 3.6 V), 12 mA (@VCC = 4.5 V to 5.5 V) Ordering Information
Package Type SOP-14 pin(JEITA) SOP-14 pin(JEDEC) TSSOP-14 pin Package Code FP-14DAV FP-14DNV TTP-14DV Package Abbreviation FP RP T Taping Abbreviation (Quantity) EL (2,000 pcs/reel) EL (2,500 pcs/reel) ELL (2,000 pcs/reel)
Part Name HD74LV74AFPEL HD74LV74ARPEL HD74LV74ATELL
Note: Please consult the sales office for the above package availability.
Function Table
Inputs PRE L H L H H H CLR H L L H H H CLK X X X D X X X H L X Outputs Q H L H*1 H L Q0 Q L H H*1 L H Q0
Note: H: High level L: Low level X: Immaterial : Low to high transition : High to low transition Q0: The level of Q immediately before the input conditions shown in the above table is determined. 1.: Q and Q will remain HIGH as long as Preset and Clear are Low, but Q and Q are unpredictable, if Preset and Clear go HIGH simultaneously.
Rev.3.00 Jun. 02, 2004 page 1 of 9
HD74LV74A
Pin Arrangement
1CLR 1 1D 1CLK 2 3
14 VCC 13 2CLR 12 2D 11 2CLK 10 2PRE 9 2Q 8 2Q
1PRE 4 1Q 1Q 5 6
GND 7
(Top view)
Absolute Maximum Ratings
Item Supply voltage range Input voltage range*1 Output voltage range*1, 2 Input clamp current Output clamp current Continuous output current Continuous current through VCC or GND Maximum power dissipation at 3 Ta = 25C (in still air)* Storage temperature Symbol VCC VI VO IIK IOK IO ICC or IGND PT Tstg Ratings -0.5 to 7.0 -0.5 to 7.0 -0.5 to VCC + 0.5 -0.5 to 7.0 -20 50 25 50 785 500 -65 to 150 Unit V V V mA mA mA mA mW C Conditions
Output: H or L VCC: OFF VI < 0 VO < 0 or VO > VCC VO = 0 to VCC
SOP TSSOP
Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The maximum package power dissipation was calculated using a junction temperature of 150C.
Rev.3.00 Jun. 02, 2004 page 2 of 9
HD74LV74A
Recommended Operating Conditions
Item Supply voltage range Input voltage range Output voltage range Output current Symbol VCC VI VO IOH Min 2.0 0 0 -- -- -- -- -- -- -- -- 0 0 0 -40 Max 5.5 5.5 VCC -50 -2 -6 -12 50 2 6 12 200 100 20 85 Unit V V V A mA Conditions
IOL
A mA
Input transition rise or fall rate
t /v
ns/V
VCC = 2.0 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 2.0 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V
Operating free-air temperature
Ta
C
Note: Unused or floating inputs must be held high or low.
Logic Diagram
PRE CLK C C C Q
TG C C C
C
D
TG
TG
TG Q
C CLR
C
C
Rev.3.00 Jun. 02, 2004 page 3 of 9
HD74LV74A
DC Electrical Characteristics
Ta = -40 to 85C Item Input voltage Symbol VIH VCC (V)* 2.0 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 2.0 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 Min to Max 2.3 3.0 4.5 Min to Max 2.3 3.0 4.5 0 to 5.5 5.5 0 3.3 Min 1.5 VCC x 0.8 VCC x 0.8 VCC x 0.8 -- -- -- -- VCC - 0.1 2.0 2.48 3.8 -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2.0 Max -- -- -- -- 0.3 VCC x 0.2 VCC x 0.2 VCC x 0.2 -- -- -- -- 0.1 0.4 0.44 0.55 1 20 5 -- Unit V Test Conditions
VIL
Output voltage
VOH
V
VOL
Input current Quiescent supply current Output leakage current Input capacitance
IIN ICC IOFF CIN
A A A pF
IOL = -50 A IOL = -2 mA IOL = -6 mA IOL = -12 mA IOL = 50 A IOL = 2 mA IOL = 6 mA IOL = 12 mA VIN = 5.5 V or GND VIN = VCC or GND, IO = 0 VI or VO = 0 V to 5.5 V VI = VCC or GND
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions.
Rev.3.00 Jun. 02, 2004 page 4 of 9
HD74LV74A
Switching Characteristics
VCC = 2.5 0.2 V Ta = 25C Item Maximum clock frequency Propagation delay time Symbol tmax tPLH tPHL Min 50 30 -- -- -- -- 8.0 7.0 0.5 8.0 8.0 Typ 100 70 9.8 11.1 13.0 14.2 -- -- -- -- -- Max -- -- 14.8 16.4 17.4 20.0 -- -- -- -- -- Ta = -40 to 85C Min 40 25 1.0 1.0 1.0 1.0 9.0 7.0 0.5 9.0 9.0 Max -- -- 17.0 19.0 20.0 23.0 -- -- -- -- -- Unit MHz ns Test Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF ns ns ns FROM (Input) TO (Output)
Setup time Hold time Pulse width
tsu th tw
PRE/CLR Q or Q CLK PRE/CLR Q or Q CLK Data PRE or CLR inactive PRE or CLR "L" CLK "H" or "L" VCC = 3.3 0.3 V
Ta = 25C Item Maximum clock frequency Propagation delay time Symbol tmax tPLH tPHL Min 80 50 -- -- -- -- 6.0 5.0 0.5 6.0 6.0 Typ 140 90 6.9 7.9 9.2 10.2 -- -- -- -- -- Max -- -- 12.3 11.9 15.8 15.4 -- -- -- -- --
Ta = -40 to 85C Min 70 45 1.0 1.0 1.0 1.0 7.0 5.0 0.5 7.0 7.0 Max -- -- 14.5 14.0 18.0 17.5 -- -- -- -- -- Unit MHz ns
Test Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF
FROM (Input)
TO (Output)
Setup time Hold time Pulse width
tsu th tw
ns ns ns
PRE/CLR Q or Q CLK PRE/CLR Q or Q CLK Data PRE or CLR inactive PRE or CLR "L" CLK "H" or "L" VCC = 5.0 0.5 V
Ta = 25C Item Maximum clock frequency Propagation delay time Symbol tmax tPLH tPHL Min 130 90 -- -- -- -- 5.0 3.0 0.5 5.0 5.0 Typ 180 140 5.0 5.6 6.6 7.2 -- -- -- -- -- Max -- -- 7.7 7.3 9.7 9.3 -- -- -- -- --
Ta = -40 to 85C Min 110 75 1.0 1.0 1.0 1.0 5.0 3.0 0.5 5.0 5.0 Max -- -- 9.0 8.5 11.0 10.5 -- -- -- -- -- Unit MHz ns
Test Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF
FROM (Input)
TO (Output)
Setup time Hold time Pulse width
tsu th tw
ns ns ns
PRE/CLR Q or Q CLK PRE/CLR Q or Q CLK Data PRE or CLR inactive PRE or CLR "L" CLK "H" or "L"
Rev.3.00 Jun. 02, 2004 page 5 of 9
HD74LV74A
Operating Characteristics
CL = 50 pF Ta = 25C Item Power dissipation capacitance Symbol CPD VCC (V) 3.3 5.0 Min -- -- Typ 21.0 23.0 Max -- -- Unit pF Test Conditions f = 10 MHz
Noise Characteristics
CL = 50 pF Ta = 25C Item Quiet output, maximum dynamic VOL Quiet output, minimum dynamic VOL Quiet output, minimum dynamic VOH High-level dynamic input voltage Low-level dynamic inout voltage Symbol VOL (P) VOL (V) VOH (V) VIH (D) VIL (D) VCC (V) 3.3 3.3 3.3 3.3 3.3 Min -- -- -- 2.31 -- Typ 0.1 0 3.2 -- -- Max 0.8 -0.8 -- -- 0.99 Unit V V V V V Test Conditions
Test Circuit
Measurement point
C L*
Note: C L includes the probe and jig capacitance.
Rev.3.00 Jun. 02, 2004 page 6 of 9
HD74LV74A
* Waveform - 1
tr 90% 50% VCC 10% t su th 90% 50% VCC
tf VCC 10% 0V
Timming input
VCC Data input 50% VCC tw VCC Input 50% VCC 50% VCC 0V 50% VCC 0V
* Waveform - 2
tr 90% 50% VCC 10% t PLH 90% 50% VCC
tf VCC 10% t PHL 0V
Input
VOH Same-phase output t PHL 50% VCC 50% VCC VOL t PLH VOH Opposite-phase output 50% VCC 50% VCC VOL
Notes: 1. Input waveform: PRR 1 MHz, Zo = 50 , tr 3 ns, tf 3 ns 2. The output are measured one at a time with one transition per measurement.
Rev.3.00 Jun. 02, 2004 page 7 of 9
HD74LV74A
Package Dimensions
As of January, 2003
Unit: mm
10.06 10.5 Max 14 8
1
7
5.5
*0.20 0.05
2.20 Max
0.20 7.80 + 0.30 -
1.42 Max
1.15 0 - 8 0.70 0.20
1.27 *0.40 0.06
0.12 M
Package Code JEDEC JEITA Mass (reference value) FP-14DAV -- Conforms 0.23 g
*Ni/Pd/Au plating
0.10 0.10
0.15
As of January, 2003
Unit: mm
8.65 9.05 Max 14 8
1
1.75 Max
*0.20 0.05
7
3.95
6.10 - 0.30 1.08
+ 0.10
0.635 Max
0 - 8
+ 0.11
1.27 *0.40 0.06
0.14 - 0.04
0.60 - 0.20
+ 0.67
0.15 0.25 M
Package Code JEDEC JEITA Mass (reference value) FP-14DNV Conforms Conforms 0.13 g
*Ni/Pd/Au plating
Rev.3.00 Jun. 02, 2004 page 8 of 9
HD74LV74A
As of January, 2003
Unit: mm
5.00 5.30 Max 14 8
1
7 0.65 1.0 0.13 M 6.40 0.20 0.83 Max 0 - 8 0.50 0.10
*0.20 0.05
4.40
*0.15 0.05
1.10 Max
0.10
0.07 +0.03 -0.04
*Ni/Pd/Au plating
Package Code JEDEC JEITA Mass (reference value)
TTP-14DV -- -- 0.05 g
Rev.3.00 Jun. 02, 2004 page 9 of 9
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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